onsemi MC100EP195FAG

32-LQFP 100EP e3 NECL MODE: VCC=0WITH VEE= -3.0V TO -3.6V delay line IC 7mm 2.2ns 3V 7Weeks

Active Delay Line, Programmable, 1-Func, 1023-Tap, Complementary Output, ECL, PQFP32

MC100EP195 Series 1.2 GHz 3.6 V SMT ECL Programmable Delay Chip - LQFP-32

Active Programmable Delay Line 1-IN 0.01ns ABS 12.2ns MAX 32-Pin LQFP Frame

No. Of Taps:32; Delay Time Per Tap:10Ps; Total Delay Time:12.2Ns; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital Ic Case:Lqfp; No. Of Pins:32Pins; Operating Temperature Min:-40°C; Operating Temperature Max:85°C Rohs Compliant: Yes |Onsemi MC100EP195FAG.

NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the data sheet logic diagram. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(0:9) which are latched on chip by a high signal on the latch enable (LEN) control. The MC10/100EP195 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in the data sheet. Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Select input pins D0-D10 may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for CMOS ECL or TTL level signals. For CMOS input levels leave VCF and VEF open. For ECL operation short VCF and VEF (pins 7 and 8). For TTL level operation connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 1.5k Ohm or 500 Ohm resistor between VCF and VEE for 3.3 V or 5.0 V power supplies respectively. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or