onsemi MC100EP14DT

3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver | IC CLK BUFFER 2:5 2GHZ 20TSSOP

Low Skew Clock Driver, 100E Series, 5 True Output(s), 0 Inverted Output(s), ECL, PDSO20

Clock Driver 2-IN ECL/PECL 20-Pin TSSOP Rail

The MC100EP14 is a low skew 1-to-5 differential driver designed with clock distribution in mind accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions. The EP14 specifically guarantees low output-to-output skew. Optimal design layout and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized both sides of any differential output need to be terminated even if only one output is being used. If an output pair is unused both outputs may be left open (unterminated) without affecting skew. The common enable (ENbar) is synchronous outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is locked on the falling edge of the input clock therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.