Texas Instruments SN74ALVC7814-40DLR

3-STATE Dual Parallel Gull Wing Asynchronous Fifo 0C~70C 3.6V 1.125K 64X 18 25MHZ
$ 5.524

Price and Stock

Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments SN74ALVC7814-40DLR.

Texas Instruments

Datasheet13 pages26 years ago

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Alternate Parts

Price @ 1000
$ 5.524
$ 11.205
$ 11.205
Stock
118,500
83,491
83,491
Authorized Distributors
2
4
4
Case/Package
SSOP
SSOP
SSOP
Number of Pins
56
56
56
Memory Size
-
144 B
144 B
Access Time
-
18 ns
18 ns
Frequency
-
25 MHz
25 MHz
Bus Directional
-
Unidirectional
Unidirectional
Programmable Flags Support
-
Yes
Yes
Retransmit Capability
-
No
No
FWFT Support
-
No
No
Min Supply Voltage
-
3 V
3 V
Max Supply Voltage
-
3.6 V
3.6 V

Related Parts

Texas InstrumentsSN74ACT7805-25DL
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY | IC CLOCKED FIFO 256X18 56-SSOP
Texas InstrumentsSN74ACT7806-40DLR
74ACT7806 Width Tape & Reel (TR) 8542.32.00.71 fifo memory 25MHz 400muA 0.635mm 40ns
Texas InstrumentsSN74ACT7805-40DLR
74ACT7805 Width Tape & Reel (TR) 8542.32.00.71 fifo memory 25MHz 400muA 0.635mm 40ns

Descriptions

Descriptions of Texas Instruments SN74ALVC7814-40DLR provided by its distributors.

3-STATE DUAL PARALLEL GULL WING Asynchronous FIFO 0C~70C 3.6V 1.125K 64x 18 25MHz
FIFO Mem Async Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R
IC MEMORY FIFO 64X18 56-SSOP / Asynchronous FIFO 1.125K (64 x 18) Uni-Directional 25MHz 20ns 56-SSOP
A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7814 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. These memories are designed for 3-V to 3.6-V VCC operation. Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 64. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect. Status of the FIFO memory is monitored by the full (FULL\), empty (EMPTY\), half-full (HF), and almost- full/almost-empty (AF/AE) flags. The FULL\ output is low when the memory is full and high when the memory is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 32 or more words and low when it contains 31 or fewer words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN\) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (64 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (63 - Y) words. A low level on the reset (RESET\) resets the internal stack pointers and sets FULL\ high, AF/AE high, HF low, and EMPTY\ low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up. The first word loaded into empty memory causes EMPTY\ to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable (OE\) is high. The SN74ALVC7814 is characterized for operation from 0C to 70C.

Manufacturer Aliases

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