Texas Instruments SN74ABT18640DLR

IC SCAN TEST DEVICE 18BIT 56SSOP / Scan Test Device
$ 10.958

Price and Stock

Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments SN74ABT18640DLR.

Texas Instruments

Datasheet32 pages18 years ago

Augswan

Sierra IC

Inventory History

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Alternate Parts

Price @ 1000
$ 10.958
$ 10.15
Stock
101,248
146,151
Authorized Distributors
2
3
Case/Package
SSOP
SSOP
Number of Pins
56
56
Logic Function
Inverting
Inverting, Transceiver
Frequency
-
-
Interface
-
-
Memory Size
-
-
Min Supply Voltage
-
4.5 V
Max Supply Voltage
-
5.5 V

Related Parts

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40¦ÌA 3 18 2 9 1.65V 3.6V 24mA Buffer,Non-Inverting 24mA SSOP-56 18.41mm*7.49mm*2.59mm
Texas InstrumentsSN74ALVCH16827DL
40¦ÌA 3 20 2 10 1.65V 3.6V 24mA Buffer,Non-Inverting 24mA SSOP-56 18.41mm*7.49mm*2.59mm
Texas Instruments74ACT16652DL
8mA 2 8 4.5V 5.5V 24mA Non-Inverting,Transceiver 24mA SSOP-56 18.41mm*7.49mm*2.59mm

Descriptions

Descriptions of Texas Instruments SN74ABT18640DLR provided by its distributors.

IC SCAN TEST DEVICE 18BIT 56SSOP / Scan Test Device
BOUNDARY SCAN TRANSCEIVER
The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ABT18640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18640 is characterized for operation from -40°C to 85°C.

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