onsemi MC100EP196BFAG

32-LQFP 100EP e3 NECL MODE: VCC=0WITH VEE=-3.0V TO -3.6V delay line circuit 7mm 2.5ns 3V 4Weeks

Active Delay Line, Programmable, 1-Func, 1023-Tap, Complementary Output, ECL, PQFP32

Active Programmable Delay Line 1-IN 0.01ns ABS 12.4ns MAX 32-Pin LQFP Frame

The MC100EP196B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tunability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram Figure 2. The delay increment of the EP196B has a digitally selectable resolution of about 10 ps and a net range of up to 10.4 ns. The required delay is selected by the 10 data select inputs D(9:0) values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D(9:0). A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D(10:0). The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.