onsemi 74LVX373M

Name: onsemi 74LVX373M
Brand: onsemi
SKU: 74LVX373M

4¦ÌA 6ns 1 2V 3.6V 4mA D-Type Transparent Latch LVX 1 4mA SOIC-20 13mm*7.6mm*2.35mm

$ 0.496

Obsolete

Manufacturer Page Datasheet

Price and Stock

Authorized Distributors

Non-Authorized Stocking Distributors

Non-Authorized Dealers

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Distributor		SKU		Min	Pkg
Avnet		74LVX373M	116,640	2500				0.398	5h
Verical	5	74LVX373M	3,124	698			0.496	0.442
Rochester Electronics	2	74LVX373M	89,444			0.478	0.397	0.354	3h
Flip Electronics		74LVX373M	29,160						3d
Farnell		74LVX373M.	0	1080	Tube			0.521*	3h

Inventory History

3 month trend: +0.00%

CAD Models

Download symbol, footprint, and 3D STEP

Alternate Parts

1 part available

Datasheets & Documents

Download datasheets and manufacturer documentation for onsemi 74LVX373M.

IHS

Datasheet7 pages21 years ago

Farnell

onsemi

TME

Augswan

Inventory History

3 month trend:

+0.00%

CAD Models

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Alternate Parts

This Part

Alternate Parts

onsemi74LVX373M

onsemi74LVX373MX

Price @ 1000

$ 0.496

$ 0.263

Stock

938,817

135,212

Authorized Distributors

Case/Package

SOP

Number of Pins

Logic Function

D-Type, Latch

Number of Elements

Number of Bits per Element

Propagation Delay

15 ns

Frequency

Clock Edge Trigger Type

Min Supply Voltage

2 V

Max Supply Voltage

3.6 V

Quiescent Current

4 µA

Supply Chain

Country of OriginTaiwan

Export Control Classification Number (ECCN) CodeEAR99

Harmonized Tariff Schedule (HTS) Code8542.39.00.01

Introduction Date1993-12-01

Lifecycle StatusObsolete (Last Updated: 11 hours ago)

LTB Date2022-01-08

LTD Date2022-07-08

Manufacturer Lifecycle StatusOBSOLETE (Last Updated: 11 hours ago)

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Descriptions

Descriptions of onsemi 74LVX373M provided by its distributors.

4¦ÌA 6ns 1 2V 3.6V 4mA D-Type Transparent Latch LVX 1 4mA SOIC-20 13mm*7.6mm*2.35mm

Unikeyic (ICkey)

74LVX373 Tube LV/LV-A/LVX/H 74LVX latch circuit 4mA 4mA 13.2ns 801mg -40C~85C

Fly-Wing Technology

Low Voltage Octal Transparent Latch with 3-STATE Outputs

onsemi

The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

Fairchild Semiconductor