onsemi 100351QC

Master Reset D-Type ECL Positive Edge Flip Flop 0C~85C TC 50mA -4.2V~-5.7V 1.8ns

Flip Flop D-Primary-Secondary Type Pos-Edge 1-Element 28-Pin PLCC Rail

-5.7V~-4.2V D-Type 6 1 375MHz PLCC-28(11.5x11.5) Flip Flops ROHS

D Flip-Flop, 100K Series, 1-Func, Positive Edge Triggered, 6-Bit, Complementary Output, ECL, PQCC28

IC FF D-TYPE SGL 6-BIT 28-PLCC

The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kohm pull-down resistors. Product Highlights: 40% power reduction of the 100151 2000V ESD protection Pin/function compatible with 100151 Voltage compensated operating range: -4.2V to -5.7V Available to industrial grade temperature range