onsemi MC10H640FNG

Low Skew Clock Driver, 10H Series, 6 True Output(s), 0 Inverted Output(s), ECL, PQCC28

Amplifiers- Audio BBG ECL/TTL Clock Driver

J BEND Obsolete ECL Lead Free 68030, 68040 MPUs IC e3 0C~85C 6ns 135MHz

Clock Divider 2-IN TTL 28-Pin PLCC Rail

The MC10H/100H640 generates the necessary clocks for the 68030 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks are typically used in present MPU systems. However as clock speeds increase to 50MHz and beyond the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its superior skew characteristic. The H640 includes divide-by-two and divide-by-four stages both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol). The 10H version is compatible with MECL 10H ECL logic levels while the 100H version is compatible with 100K levels (referenced to +5.0V).