1,443 results found for "latching buffer"
clock. Taking high disables the clock buffer, thus latching the outputs. Taking the clear () input low causes the eight Q outputs to go low
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops are edge
. Taking high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has
. Taking high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has
. Taking high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has
DistributorSKUMOQPkgBulk PricingUpdated
542338710USD
6d
SN74AS823ADWR2,440
>1wk
SN74AS823ADWRYes
>1wk
3-CH LCD Bias w/ GPM VCOM Buffer & Gate Driver for Isolation Switch
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output
. The AD7237A has a double buffered interface structure and an 8-bit wide data bus with data loaded to the respective input latch in two write
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output