onsemi MC100LVEL51DG

MC Series 3.3 V Surface Mount ECL Differential Clock D Flip-Flop - SOIC-8

Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 1-Element 8-Pin SOIC N Tube

D-Type Flip Flop, 0.475Ns, Soic-8; Tipo De Flip-Flop:D; Retardo De Propagación:475Ps; Tensión De Alimentación Mín.:3V; Tensión De Alimentación Máx.:3.8V; Circuito Lógico, Tipo:Soic; Núm. De Contactos:8; Frecuencia:2.8Ghz |Onsemi MC100LVEL51DG

The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51 the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V VCC. The reset input is an asynchronous level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave and thus the outputs upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC/2.