1: 3 LVPECL clock buffer & LVCMOS output & programmable divider 24-VQFN -40 to 85

1: 3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider 24-VQFN -40 to 85

1: 3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider 24-VQFN -40 to 85

CML HSTL LVDS LVPECL LVTTL SSTL-2VML CDCM1804 24-VFQFN Exposed Pad Active clock driver 4mm 3.3V 0.6ns 800MHz

1: 3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider 24-VQFN -40 to 85

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0]