Texas Instruments SN74V293-7PZA

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
$ 30.353
Production

Price and Stock

Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments SN74V293-7PZA.

HQonline

Datasheet52 pages17 years ago

Texas Instruments

Sierra IC

SHENGYU ELECTRONICS

Inventory History

3 month trend:
-17.68%

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Alternate Parts

Price @ 1000
$ 30.353
$ 77.88
$ 77.88
Stock
143,341
145,896
145,896
Authorized Distributors
2
2
2
Case/Package
LQFP
LQFP
LQFP
Number of Pins
80
80
80
Memory Size
144 kB
144 kB
144 kB
Access Time
5 ns
5 ns
5 ns
Frequency
133 MHz
133 MHz
133 MHz
Bus Directional
Unidirectional
Unidirectional
Unidirectional
Programmable Flags Support
-
Yes
Yes
Retransmit Capability
-
Yes
Yes
FWFT Support
-
Yes
Yes
Min Supply Voltage
3.15 V
3.15 V
3.15 V
Max Supply Voltage
3.45 V
3.45 V
3.45 V

Supply Chain

Lifecycle StatusProduction (Last Updated: 4 days ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 4 days ago)

Related Parts

Texas InstrumentsSN74V293PZAEP
Enhanced Product 65536 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Texas InstrumentsSN74V263PZAEP
Enhanced Product 8192 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Texas InstrumentsSN74V283PZAEP
Enhanced Product 32768 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
4Kx18 6.5ns 30mA 3V~3.6V 100MHz TQFP-64(10x10) FIFO Memory ROHS
32Kx18 6.5ns 60mA 3V~3.6V 100MHz TQFP-64(10x10) FIFO Memory ROHS
QUAD COMMERCIAL PARALLEL Tin (Function) FIFO 0C 3.6V 2.3kB 10ns

Descriptions

Descriptions of Texas Instruments SN74V293-7PZA provided by its distributors.

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
ACTIVE (Last Updated: 3days ago) 74V293 Depth Width Tray fifo memory 133MHz 35mA 0.65mm 7.5ns
65536 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching *9/*18 data flow. There is flexible *9/*18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins' input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Copyright (C) 2003, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Manufacturer Aliases

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