Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70

AND 74LS11 EAR99 74LS logic gate circuit 20ns @ 5V 15pF 1.75mm 400muA 8mA 2V

AND 74LS11 EAR99 74LS logic gate circuit 20ns @ 5V 15pF 2mm 400muA 8mA 2V

AND 74LS11 EAR99 74LS logic gate circuit 20ns @ 5V 15pF 1.75mm 400muA 8mA 2V

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70

AND Gate, LS Series, 3-Func, 3-Input, TTL, PDSO14

Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOP T/R

Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP Tube