STMicroelectronics HCF4021BEY

4000/14000/40000 Series 8-BIT Right Parallel in Serial Out Shift Register True Output PDIP16

Shift Register Single 8-Bit Serial/Parallel to Parallel 16-Pin PDIP Tube

HCF4021 Non-RoHS Compliant Tube e4 shift register 320ns 1muA 5.1mm 17MHz

IC, 4000 CMOS, 4021, DIP16, 15V; Shift Register Function:Parallel to Serial, Serial to Serial; Logic Type:Shift Register; No. of Elements:1; IC Output Type:Standard; Logic Case Style:DIP; No. of Pins:16; Supply Voltage Range:3V to 20V; Operating Temperature Range:-55°C to +125°C; SVHC:No SVHC (20-Jun-2011); Base Number:4021; Frequency:17MHz; IC Generic Number:4021; Input Current Max:1µA; Logic Function Number:4021; Logic IC Base Number:4021; Logic IC Family:4000 CMOS; Logic IC Function:8bit Static Shift Register; No. of Gates:1; Operating Temperature Max:125°C; Operating Temperature Min:-55°C; Output Type:Standard; Package / Case:DIP; Power Dissipation Ptot Max:200mW; Shift Register Function:Parallel or Serial In / Serial Out; Supply Voltage:15V; Supply Voltage Max:15V; Supply Voltage Min:3V; Termination Type:Through Hole

The HCF4021B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/ serial output register having common CLOCK andPARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM"inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. In this device, entry is controlled by thePARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, datais serially shifted into the 8-stage register synchronously with the positive transition of heclock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the8-stage register via the parallel input lines and synchronous with the positive transition of the clock line, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple package is permitted.