onsemi 74VHC112MX

Tape & Reel (TR) 74VHC112 e3 74VHC flip flop 9.9mm 2V 10.5ns @ 5V 50pF 185MHz

Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC N T/R

74VHC112 Series 5.5 V Dual J-K Flip-Flop - SOIC-16

Ic, flip-Flop, dual, j/K Type, ahc/Vhc-Cmos, sop,16Pin, plastic Rohs Compliant: Yes |Onsemi 74VHC112MX

J-K Flip-Flop, AHC/VHC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16

IC FF JK TYPE DUAL 1BIT 16SOIC

Dual J-K Flip-Flops with Preset and Clear

J-K FLIP-FLOP, AHC/VHC SERIES, 2

IC FF JK TYPE DBL 1-BIT 16-SOIC

IC JK TYPE NEG TRG DUAL 16SOIC

The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q# HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q# HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.