877 Series Pll Based Clock Driver 10 True Output(s) 0 Inverted Output(s) PBGA52

1.8-V phase-lock loop clock driver with high output drive for DDR2 SDRAM applications 52-NFBGA 0 to 70

1.8-V phase-lock loop clock driver with high output drive for DDR2 SDRAM applications 52-NFBGA 0 to 70

The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CKYnFBOUTCKFBINFBOUTY7CKFBINCK

PLL Based Clock Driver, 877 Series, 10 True Output(s), 0 Inverted Output(s), PBGA52