PLL Clock Driver Single 25MHz to 125MHz 24-Pin TSSOP T/R

3.3V Phase Lock Loop Clock Driver 24-TSSOP 0 to 70

the cdc509 is a high-performance low-skew low-jitter phase-lock loop (pll) clock driver. it uses a pll to precisely align in both frequency and phase

operation from 0C to 85C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510

from 0C to 85C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516

information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

PLL Based Clock Driver, CDC Series, 9 True Output(s), 0 Inverted Output(s), PDSO24