Texas Instruments CD74FCT273M96E4

Tape & Reel (TR) 74FCT273 74FCT Non-Inverting flip flop 2.65mm 4.75V 7ns @ 5V 50pF 70MHz

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Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments CD74FCT273M96E4.

Texas Instruments

Datasheet11 pages18 years ago

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Alternate Parts

Price @ 1000
$ 0.589
$ 0.589
Stock
65,385
656,358
656,358
Authorized Distributors
0
4
4
Case/Package
SOIC
SOIC
SOIC
Number of Pins
20
20
20
Logic Function
D-Type, Flip-Flop
D-Type
D-Type
Number of Elements
1
1
1
Number of Bits per Element
8
8
8
Propagation Delay
7 ns
13 ns
13 ns
Frequency
70 MHz
-
-
Clock Edge Trigger Type
Positive Edge
Positive Edge
Positive Edge
Min Supply Voltage
4.75 V
4.75 V
4.75 V
Max Supply Voltage
5.25 V
5.25 V
5.25 V
Quiescent Current
-
-
-

Descriptions

Descriptions of Texas Instruments CD74FCT273M96E4 provided by its distributors.

Tape & Reel (TR) 74FCT273 74FCT Non-Inverting flip flop 2.65mm 4.75V 7ns @ 5V 50pF 70MHz
IC FF D-TYPE SNGL 8BIT 20SOIC
IC D-TYPE POS TRG SNGL 20SOIC
20 LEAD SOIC(300MIL) <AZ
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR\) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR\). The outputs are placed in a low state when CLR\ is taken low, independent of the CLK. The CD74FCT273 is characterized for operation from 0C to 70C.

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