Renesas ISL89165FBEBZ

ISL89165 Series Dual Ch 6 A 2 Ohm 0 to 16 Vout Power MOSFET Driver - SOIC-8
$ 2.668
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Integrated Device Technology

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Modellinformationen
Beschafft vonRenesas
VeröffentlichungsdatumAug 13, 2025
IPC-konformIPC-7351B
Überarbeitung des StyleguidesVersion 1.0 - Nov 1, 2024
DatenblattquelleVersion 6.00 - Jul 9, 2019
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Country of OriginMalaysia
Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8540000000
Introduction Date2010-10-12
Lifecycle StatusProduction (Last Updated: 2 months ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 2 months ago)

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Beschreibungen

Beschreibungen von Renesas ISL89165FBEBZ, die von den Distributoren bereitgestellt werden.

ISL89165 Series Dual Ch 6 A 2 Ohm 0 to 16 Vout Power MOSFET Driver - SOIC-8
GULL WING RoHS Compliant Active Matte Tin (Sn) - annealed IC Gate Driver 3.9mm 16V 33.3W 6A
High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs
Gate Driver, Mosfet, 2-Ch, Nsoic-Ep-8 Rohs Compliant: Yes |Renesas Electronics Corporation ISL89165FBEBZ
The ISL89163, ISL89164, and ISL89165 are high-speed, 6A, dual channel MOSFET drivers with enable inputs. Precision thresholds on all logic inputs allow the use of external RC circuits to generate accurate and stable time delays on both the main channel inputs, INA and INB, and the enable inputs, ENA and ENB. The precision delays capable of these precise logic thresholds makes these parts very useful for dead-time control and synchronous rectifiers. Note that the enable and input logic inputs can be interchanged for alternate logic implementations. Three input logic thresholds are available: 3. 3V (CMOS), 5. 0V (CMOS or TTL compatible), and CMOS thresholds that are proportional to VDD. At high switching frequencies, these MOSFET drivers use very little internal bias currents. Separate, non-overlapping drive circuits are used to drive each CMOS output FET to prevent shoot-through currents in the output stage. The start-up sequence is designed to prevent unexpected glitches when VDD is being turned on or turned off. When VDD < ~1V, an internal 10kΩ resistor between the output and ground helps to keep the output voltage low. When ~1V < VDD < UV, both outputs are driven low with very low resistance and the logic inputs are ignored. This insures that the driven FETs are off. When VDD > UVLO, and after a short delay, the outputs now respond to the logic inputs.

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