onsemi MC100LVEP34DG

MC100LVEP34 Series 2.8 GHz 3.8 V ECL ÷2, ÷4, ÷8 Clock Generation Chip - SOIC-16

Low Skew Clock Driver, 100LVE Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO16

IC, CLOCK GENERATION CHIP, 2.8GHZ SOIC16

CML LVDS NECL PECL Clock Generator 16-SOIC (0.154 3.90mm Width) MC100LVEP34 clock generator ic 2.42V 2.8GHz 50mA 52mA

Clock Generator 16-Pin SOIC Rail

2.375V 3.8V 2.8GHz SOIC-16 3.9mm*1.5mm

The MC100LVEP34 is a low skew DIV2 DIV4 DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore all associated specification limits are referenced to the negative edge of the clock input. Upon startup the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a VCC of = 3.0 V in PECL mode or VEE = -3.0 V in NECL mode.