onsemi MC10EL34DG

MC10EL34 Series 5.7 V 1.1 GHz SMT ECL ÷2, ÷4, ÷8 Clock Generation Chip -SOIC-16

5V ECL DIVIDED BY 2, DIVIDED BY 4, DIVIDED BY 8 CLOCK GENERATION CHIP Low Skew Clock Driver, 10EL Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO16

The MC10/100EL34 is a low skew divide by 2 divide by 4 divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or if positive power supplies are used PECL input signal. In addition by using the VBB output a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions as a result this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock therefore all associated specification limits are referenced to the negative edge of the clock input. Upon startup the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers as well as multiple EL34s in a system. The 100 Series contains temperature compensation.