Texas Instruments SN74LVC841ADWR

IC 10BIT BUS INT D LATCH 24-SOIC / D-Type Transparent Latch 1 Channel 10: 10 IC Tri-State 24-SOIC

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Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments SN74LVC841ADWR.

Texas Instruments

Datasheet15 pages18 years ago

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Alternate Parts

Price @ 1000
$ 1.271
$ 1.271
Stock
133,921
288,339
288,339
Authorized Distributors
0
5
5
Case/Package
SOIC
SOIC
SOIC
Number of Pins
24
24
24
Logic Function
D-Type, Latch
D-Type, Latch
D-Type, Latch
Number of Elements
1
1
1
Number of Bits per Element
-
-
-
Propagation Delay
6.7 ns
6.7 ns
6.7 ns
Frequency
-
-
-
Clock Edge Trigger Type
-
-
-
Min Supply Voltage
1.65 V
1.65 V
1.65 V
Max Supply Voltage
3.6 V
3.6 V
3.6 V
Quiescent Current
-
-
-

Descriptions

Descriptions of Texas Instruments SN74LVC841ADWR provided by its distributors.

IC 10BIT BUS INT D LATCH 24-SOIC / D-Type Transparent Latch 1 Channel 10:10 IC Tri-State 24-SOIC
IC 10BIT BUS INT D LATCH 24-SOIC
LVC/LCX/Z SERIES 10-BIT DRIVER TRUE OUTPUT PDSO24
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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