Texas Instruments SN74ABT8543DWR

IC SCAN TEST DEVICE 28-SOIC / Scan Test Device with Registered Bus Transceiver IC 28-SOIC

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Datasheets & Documents

Download datasheets and manufacturer documentation for Texas Instruments SN74ABT8543DWR.

Texas Instruments

Datasheet33 pages18 years ago

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Alternate Parts

Price @ 1000
$ 10.181
Stock
128,681
236,640
Authorized Distributors
0
2
Case/Package
SOIC
SOIC
Number of Pins
-
28
Logic Function
Transceiver
Transceiver
Number of Circuits
-
8
Number of Inputs
-
-
Number of Outputs
-
8
Propagation Delay
-
13.5 ns
Low Level Output Current
-
-
High Level Output Current
-
-
Min Supply Voltage
-
4.5 V
Max Supply Voltage
-
5.5 V

Descriptions

Descriptions of Texas Instruments SN74ABT8543DWR provided by its distributors.

IC SCAN TEST DEVICE 28-SOIC / Scan Test Device with Registered Bus Transceiver IC 28-SOIC
The 'ABT8543 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. In the normal mode, these devices are functionally equivalent to the 'F543 and 'ABT543 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers. Data flow in each direction is controlled by latch-enable ( and ), chip-enable ( and ), and output-enable ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when and are both low. When either or is high, the A data is latched. The B outputs are active when and are both low. When either or is high, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses , , and . In the test mode, the normal operation of the SCOPETM registered bus transceiver is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990. Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT8543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8543 is characterized for operation from -40°C to 85°C.

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