onsemi MC10E451FNG

D Flip-Flop, 10E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28

Lead Free Not Qualified Master Reset D-Type Flip Flop 0C~85C TA 101mA -4.2V~-5.7V 1.05ns

Flip Flop D-Type Bus Interface Pos-Edge/Neg-Edge 1-Element 28-Pin PLCC Rail

The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The 100 Series contains temperature compensation.