Texas Instruments SN74ALS229BDW

74ALS229 Width Tube 8542.32.00.71 fifo memory 40MHz 140mA 1.27mm 25ns
$ 4.016
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Texas Instruments

Datasheet12 pagesIl y a 18 ans

Newark

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Pièces de rechange

Price @ 1000
$ 4.016
$ 4.016
Stock
50,355
96,904
Authorized Distributors
2
2
Case/Package
SOIC
SOIC
Number of Pins
20
-
Memory Size
-
-
Access Time
-
-
Frequency
40 MHz
-
Bus Directional
-
-
Programmable Flags Support
-
-
Retransmit Capability
-
-
FWFT Support
-
-
Min Supply Voltage
-
-
Max Supply Voltage
-
-

Pièces détachées

Texas InstrumentsSN74ALS232BDW
ACTIVE (Last Updated: 1week ago) 74ALS232 Width Tube fifo memory 40MHz 125mA 2.65mm 30ns
Texas InstrumentsCD74HCT40105M
High Speed CMOS Logic 4-Bit by 16-Word FIFO egister 16-SOIC -55 to 125
Texas InstrumentsCD74HC40105M96
High Speed CMOS Logic 4-Bit by 16-Word FIFO egister 16-SOIC -55 to 125
Texas InstrumentsCD74HC40105M
High Speed CMOS Logic 4-Bit by 16-Word FIFO egister 16-SOIC -55 to 125
Texas InstrumentsCD74HCT40105MT
High Speed CMOS Logic 4-Bit by 16-Word FIFO Register 16-SOIC -55 to 125
Texas InstrumentsCD74HC40105MT
High Speed CMOS Logic 4-Bit by 16-Word FIFO Register 16-SOIC -55 to 125

Descriptions

Descriptions de Texas Instruments SN74ALS229BDW fournies par ses distributeurs.

74ALS229 Width Tube 8542.32.00.71 fifo memory 40MHz 140mA 1.27mm 25ns
FIFO Logic IC; Logic Family:ALS; Frequency Max:40MHz; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-SOIC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
This 80-bit memory uses advanced low-power Schottky technology and features high speed and fast fall-through times. It is organized as 16 words by 5 bits. A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates from 0 to 40MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK). The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the FULL\, EMPTY\, (FULL-2)\, and (FULL+2)\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The (FULL-2)\ output is low when the memory contains 14 data words. The EMPTY\ output is low when the memory is empty and high when it is not empty. The (EMPTY+2)\ output is low when two words remain in memory. A low level on the reset (RST\) input resets the internal stack control pointers and also sets EMPTY\ low and sets FULL\, (FULL-2)\, and (EMPTY+2)\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK after either a RST\ pulse or from an empty condition causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS229B is characterized for operation from 0C to 70C.

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