onsemi MC100E111FNG

5.0 V ECL 1:9 Differential Clock/Data Fanout Buffer

Clock Buffer, Driver, Fanout, 9 Outputs, 4.2 V to 5.7 V, 28 Pins, PLCC

MC100E111 Series 800 MHz 5.7 V ECL 1:9 Differential Clock Driver - PLCC-28

Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28

Clock Fanout Buffer 9-OUT 1-IN 1:9 28-Pin PLCC Tube

Clock Ic Type:Clock Driver; Frequency:800Mhz; No. Of Outputs:9Outputs; Supply Voltage Min:4.2V; Supply Voltage Max:5.7V; Clock Ic Case Style:Lcc; No. Of Pins:28Pins; Operating Temperature Min:-40°C; Operating Temperature Max:85°C Rohs Compliant: Yes |Onsemi MC100E111FNG.

NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V ECL PECL MC100E111 28-LCC (J-Lead) clock buffer 4.57mm 45mA 0.075ns 800MHz

The MC10E/100E111 is a low skew 1-to-9 differential driver designed with clock distribution in mind. It accepts one signal input which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Qbar outputs HIGH. The device is specifically designed modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO ) as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used which while not being catastrophic to most designs will mean a loss of skew margin. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The 100 Series contains temperature