Analog Devices AD800-52BRZ

PLL Clock Generator Single 51.84MHz 20-Pin SOIC W

20-SOIC (0.295 7.50mm Width) DS-3STS-1 AD800 PRODUCTION (Last Updated: 3weeks ago) application specific IC 7.6mm 180mA -5.5V 51.84MHz

CLK REC/DATA RETIMING, 51.84MHZ, WSOIC20; Clock IC Type:Clock & Data Recovery; Frequency:51.84MHz; No. of Outputs:1Outputs; Supply Voltage Min:-5.5V; Supply Voltage Max:-4.5V; Clock IC Case Style:WSOIC; No. of Pins:20Pins RoHS Compliant: Yes

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data re timing on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155. Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop than acquires the phase of the input data, and ensures the phase of the output signals track changes in the phase of the output data. The loop damping of the circuit is dependent of the value of a user selected capacitor; this defines jitter peaking and performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 X 105 bit periods when using a damping factor of 5. During the process of acquisition the frequency detector provides a Frequency Acquisition (FRAC) signal which indicates that the device has not yet locked onto the input data. This signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. Once the circuit has acquired frequency lock no pulses occur at the FRAC output. The inclusion of a precisely trimmed VCO in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components. The VCO provides a clock output within ±20% of the device center frequency in the absence of input data. The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. Total loop jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask programmable fractional loop bandwidth. The AD800, used for data rates <90 Mbps, has been designed with nominal loop bandwidth of 0.1% of the center frequency. The AD802, used for data rates in excess of 90 Mbps, has a loop bandwidth of 0.08% of center frequency. All of the devices operate with a single +5 V or -5.2 V supply.