STMicroelectronics HCF4021M013TR

HCF4021 ROHS3Compliant Tape & Reel (TR) e4 shift register 120ns 1.65mm 3V -55C~125C
Obsolete
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SHENGYU ELECTRONICS

Datasheet13 SeitenVor 13 Jahren

IHS

Components Direct

Future Electronics

iiiC

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Alternative Teile

Price @ 1000
$ 0.277
$ 0.277
Stock
262,034
857,198
857,198
Authorized Distributors
0
6
6
Case/Package
SOP
SOP
SOP
Number of Pins
16
16
16
Logic Function
OR, Shift Register
OR, Shift Register
OR, Shift Register
Direction
Unidirectional
Unidirectional
Unidirectional
Number of Elements
1
1
1
Number of Bits per Element
8
8
8
Propagation Delay
320 ns
800 ns
800 ns
Min Supply Voltage
3 V
3 V
3 V
Max Supply Voltage
20 V
18 V
18 V

Lieferkette

Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1980-01-04
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2013-08-14
LTD Date2013-08-14

Beschreibungen

Beschreibungen von STMicroelectronics HCF4021M013TR, die von den Distributoren bereitgestellt werden.

HCF4021 ROHS3Compliant Tape & Reel (TR) e4 shift register 120ns 1.65mm 3V -55C~125C
Shift Register Single 8-Bit Serial/Parallel to Parallel 16-Pin SOP T/R
ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS SERIAL IN / SERIAL OUT 8-STAGE STATIC SHIFT REGISTER Parallel In Serial Out, 4000/14000/40000 Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16
The HCF4021B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is an 8-stage parallel or serial input/ serial output register having common CLOCK andPARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM"inputs to each register stage. Each register stage is a D-type, master-slave flip-flop in addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. In this device, entry is controlled by thePARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, datais serially shifted into the 8-stage register synchronously with the positive transition of heclock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the8-stage register via the parallel input lines and synchronous with the positive transition of the clock line, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple package is permitted.

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  • SGST
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  • WAFERSCALE INTEGRATION INC
  • SGS-Thomson Microelectronics
  • ST Microeletronics