onsemi MC100E404FNG

MC100E404FNG, Quad 2-INPUT And/nand Logic Gate, 4.2 - 5.7 V, 28-PIN Plcc
$ 6.2
Obsolete
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IHS

Datasheet7 SeitenVor 9 Jahren

SHENGYU ELECTRONICS

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Alternative Teile

Price @ 1000
$ 6.2
$ 6.919
$ 6.919
Stock
98,330
119,831
119,831
Authorized Distributors
3
2
2
Case/Package
PLCC
PLCC
PLCC
Number of Pins
28
28
28
Logic Function
AND, NAND
AND, NAND
AND, NAND
Number of Circuits
4
4
4
Number of Inputs
2
2
2
Propagation Delay
725 ps
725 ps
725 ps
Low Level Output Current
50 mA
50 mA
50 mA
High Level Output Current
-50 mA
-50 mA
-50 mA
Min Supply Voltage
4.2 V
4.2 V
4.2 V
Max Supply Voltage
5.7 V
5.7 V
5.7 V
Quiescent Current
106 mA
106 mA
106 mA

Lieferkette

Country of OriginPhilippines
Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1993-12-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2017-01-22
LTD Date2017-07-22

Verwandte Teile

ECL Quad Differential AND/NAND Gate
0.725ns 2 10 4 4 4.2V 5.7V 50mA AND,NAND Gate ECL -50mA PLCC-28 , 11.58mm*11.58mm*3.69mm
QUAD DIFFERENTIAL AND/NAND | IC GATE AND/NAND QD DIFF 28-PLCC

Beschreibungen

Beschreibungen von onsemi MC100E404FNG, die von den Distributoren bereitgestellt werden.

MC100E404FNG, QUAD 2-INPUT AND/NAND LOGIC GATE, 4.2 - 5.7 V, 28-PIN PLCC
OPEN-EMITTER Tin (Sn) 100E AND/NAND Gate multiple gates 4.57mm 700ps 5V -50mA
ECL Quad Differential AND/NAND Gate
AND/NAND Gate, 100E Series, 4-Func, 2-Input, ECL, PQCC28
The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. Because a negative 2-input NAND function is equivalent to a 2-input OR function the differential inputs and outputs of the device also allow for its use as a fully differential 2 input OR/NOR function. The output RISE/FALL times of this device are significantly faster than most other standard ECLinPS devices resulting in an increased bandwidth. The differential inputs have clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC. The 100 Series contains temperature compensation.

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