onsemi MC100E196FNG

Surface Mount Programmable Lead Free Obsolete delay line IC 0C~85C 2006 4.2V~5.7V 1.39ns
$ 3.07
Obsolete
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Datasheet12 SeitenVor 19 Jahren

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Alternative Teile

Price @ 1000
$ 3.07
$ 3.07
$ 3.07
Stock
29,283
106,384
106,384
Authorized Distributors
1
1
1
Propagation Delay
3.63 ns
3.63 ns
3.63 ns
Number of Taps
127
127
127
Turn-On Delay Time
-
-
-
Frequency
-
-
-
Load Capacitance
-
-
-
Interface
-
-
-
Min Supply Voltage
4.2 V
4.2 V
4.2 V
Max Supply Voltage
5.7 V
5.7 V
5.7 V
Number of Channels
-
-
-
Case/Package
PLCC
PLCC
PLCC
Number of Pins
28
28
28

Lieferkette

Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1993-12-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2007-12-31
LTD Date2008-06-30

Verwandte Teile

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MicrochipSY100E111AJY
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE) | IC CLK BUFFER 1:9 28PLCC
Analog DevicesDS1685Q-5+T&R
parallel connection PLCC-28(11.5x11.5) Real-time Clocks (RTC) ROHS
Texas InstrumentsCGS2535VX
CMOS CGS2535 28-LCC (J-Lead) Obsolete clock driver 3V~5.25V 5ns 125MHz 0C~70C

Beschreibungen

Beschreibungen von onsemi MC100E196FNG, die von den Distributoren bereitgestellt werden.

Surface Mount Programmable Lead Free Obsolete delay line IC 0C~85C 2006 4.2V~5.7V 1.39ns
Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28
Skew Management, 5.0 V, ECL Programmable Delay Chip
IC DELAY LINE 128TAP PROG 28PLCC
ACTIVE DELAY LINE, PROGRAMMABLE
Programmable Logic IC; Logic Type:Programmable; Package/Case:28-PLCC; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:0 C; Peak Reflow Compatible (260 C):Yes; Supply Voltage Nom, Vcc:5V RoHS Compliant: Yes
The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6] which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input D7 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs at the expense of only a single added line to the data bus for each additional PDC without the need for any external gating. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The 100 Series contains temperature compensation.

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