Texas Instruments SN74ABT7819-20PN

512 x 18 x 2 bidirectional synchronous FIFO memory 80-LQFP 0 to 70

FIFO Mem Sync Dual Bi-Dir 512 x 18 x 2 80-Pin LQFP

IC SYNC FIFO MEM 512X18X2 80LQFP

IC MCU 32BIT 2MB FLASH 100LQFP

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7819 is a high-speed, low-power Bi CMOS bidirectional clocked FIFO memory. Two independent 512 * 18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag. The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The state of the A0-A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs are active. The A0-A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data is written to FIFOA-B from port A on the low-to-high transition of CLKA when CSA is low, W/RA is high, WENAis high, and the IRA flag is high. Data is read from FIFOB-A to the A0-A17 outputs on the low-to-high transition of CLKA when CSA is low, W/RA is low, RENA is high, and the ORA flag is high.