Texas Instruments LMK61E2-100M00SIAR

Name: Texas Instruments LMK61E2-100M00SIAR
Brand: Texas Instruments
SKU: LMK61E2-100M00SIAR

100-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator 6-QFM -40 to 85

$ 4.564

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Distributor	SKU		Min	Pkg
Arrow Electronics	LMK61E2-100M00SIAR	0	2500						6.216
Component Stockers USA	LMK61E2-100M00SIAR	25,834			7.060	6.920	6.700	4.270	6.500	7d
Worldway Electronics	LMK61E2-100M00SIAR	24,972	7	Tape & Reel		2.567	2.488	2.357	2.357	23h
Esaler Electronic	LMK61E2-100M00SIAR	2,500			5.705	5.648	5.592	5.537	5.482	24m
Fmall Co., Limited	LMK61E2-100M00SIAR	39,110			3.728	3.728	3.488	3.287	3.007	1d

数据表和文档

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Texas Instruments

Technical Drawing2 页9 年前

Official datasheet0 页0 年前

Technical Drawing4 页10 年前

Datasheet5 页10 年前

HQonline

SHENGYU ELECTRONICS

库存历史记录

3 个月趋势:

+0.00%

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Texas InstrumentsLMK61E2-100M00SIAR

Texas InstrumentsLMK61E2-100M00SIAT

Price @ 1000

$ 4.564

$ 6.9

Stock

215,188

111,010

Authorized Distributors

Case/Package

SMD/SMT

Number of Pins

Logic Function

Frequency

100 MHz

Interface

Memory Size

Min Supply Voltage

3.135 V

Max Supply Voltage

3.465 V

供应链

Lifecycle StatusProduction (Last Updated: 4 days ago)

Manufacturer Lifecycle StatusACTIVE (Last Updated: 4 days ago)

工程资源

查看 Texas Instruments LMK61E2-100M00SIAR 的评估工作包和参考设计。

评估工具包

LMK61E2-100M00SIAR 评估工具包

参考设计

12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

18-bit: 2-Msps Isolated Data Acquisition Reference Design to Achieve Maximum SNR and Sampling Rate

20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI

20-bit: 1-MSPS Isolator Optimized Data Acquisition Reference Design Maximizing SNR and Sample Rate

9.8GHz RF CW Signal Generator Using Integrated Synthesizer With Spur Reduction Reference Design

ADC Driver Reference Design Improving Full Scale THD Using Negative Supply

ADC Voltage Reference Buffer Optimization Reference Design for High Performance DAQ Systems

Flexible 3.2-GSPS multi-channel AFE reference design for DSOs: radar and 5G wireless test systems

High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

描述

由其分销商提供的 Texas Instruments LMK61E2-100M00SIAR 的描述。

100-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator 6-QFM -40 to 85

Texas Instruments

Clock Oscillator LVPECL ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT LMK61E2 programmable timer -40C~85C 0.2ns 3.3V 3 (168Hours)

Fly-Wing Technology

LVPECL; Mounting Feature: SURFACE MOUNT; No. of Terminals: 6; Frequency Stability: 50 %; Frequency Adjustment (Mechanical): NO; Maximum Operating Temperature: 85 Cel;

Semicontronic