This device is designed for low level analog switching, sample and hold circuits and chopper stabalized amplifiers. Sourced from Process 51. See J111 for characteristics.
JFET, N-CH, -40V, SOT-23; Breakdown Voltage Vbr:-40V; Zero Gate Voltage Drain Current Idss Min:8mA; Zero Gate Voltage Drain Current Idss Max:-; Gate-Source Cutoff Voltage Vgs(off) Max:-5V; Transistor Case Style:SOT-23; T