onsemi MC74VHC74DR2G

Name: onsemi MC74VHC74DR2G
Brand: onsemi
SKU: MC74VHC74DR2G

74VHC Series Dual Type-D Flip-Flop with Set and Reset SMT - SOIC 14

$ 0.149

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Distributor		SKU		Min	Pkg
Newark	2	MC74VHC74DR2G	1,546	5	Cut Tape		0.221	0.176	0.176	0.176
Verical	7	MC74VHC74DR2G	2,297	28				0.120	0.114	0.114
Arrow Electronics	2	MC74VHC74DR2G	2,297	1		0.339	0.319	0.264	0.252	0.252
Rochester Electronics		MC74VHC74DR2G	22,589					0.167	0.139	0.124	4h
DigiKey	3	MC74VHC74DR2GOSCT-ND	9,153	1	Cut Tape	0.340	0.236	0.181	0.152	0.152

数据表和文档

下载 onsemi MC74VHC74DR2G 的数据表和制造商文档。

IHS

Datasheet8 页7 年前

Master Electronics

onsemi

Future Electronics

iiiC

库存历史记录

3 个月趋势:

+18.72%

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onsemiMC74VHC74DR2G

onsemiMC74VHC74DR2

Price @ 1000

$ 0.149

$ 0.077

Stock

574,528

390,734

Authorized Distributors

Case/Package

SOP

Number of Pins

Logic Function

AND, D-Type, Flip-Flop

Number of Elements

Number of Bits per Element

Propagation Delay

10.5 ns

Frequency

75 MHz

Clock Edge Trigger Type

Positive Edge

Min Supply Voltage

2 V

Max Supply Voltage

5.5 V

Quiescent Current

2 µA

供应链

Country of OriginMainland China, Philippines, Thailand

Harmonized Tariff Schedule (HTS) Code8542.39.00.60

Introduction Date1997-06-01

Lifecycle StatusProduction (Last Updated: 5 years ago)

Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

描述

由其分销商提供的 onsemi MC74VHC74DR2G 的描述。

74VHC Series Dual Type-D Flip-Flop with Set and Reset SMT - SOIC 14

Future Electronics

Flip Flop D-Type Pos-Edge 2-Element Automotive 14-Pin SOIC N T/R

Verical

Tape & Reel (TR) 74VHC74 e3 74VHC flip flop 8.65mm 2V 9.3ns @ 5V 50pF 115MHz

Fly-Wing Technology

D FLIP FLOP W/ SET/RESET, DUAL, SOIC-14; Logic Family / Base Number: 74VHC74; Flip-Flop Type: D; Propagation Delay: 9.3ns; Frequency: 170MHz; Output Current: -; Logic Case Style: SOIC; No. of Pins: 14Pins; Trigger Type: Positive

Farnell

The MC74VHC74 is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

North Star Micro