onsemi MC74AC74DG

Name: onsemi MC74AC74DG
Brand: onsemi
SKU: MC74AC74DG

4¦ÌA 10ns@ 5V, 50pF , 2 2V 6V 24mA Set(Preset) and Reset AC 4.5pF 24mA 160MHz SOIC-14 1.75mm

$ 0.282

Production

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价格与库存

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Distributor		SKU		Min	Pkg
Avnet		MC74AC74DG	3,455	55		0.174	0.161	0.161	1d
Newark	2	MC74AC74DG	3,455	55		0.430	0.310	0.285
Verical	9	MC74AC74DG	27,123	1118				0.299
Future Electronics	2	MC74AC74DG	1,427	125	Tube		0.170	0.163
Rochester Electronics		MC74AC74DG	151,088			0.324	0.269	0.239	15m

数据表和文档

下载 onsemi MC74AC74DG 的数据表和制造商文档。

IHS

Datasheet11 页11 年前

Farnell

RS (Formerly Allied Electronics)

库存历史记录

3 个月趋势:

-0.45%

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onsemiMC74AC74DG

onsemiMC74AC74DR2G

Price @ 1000

$ 0.282

$ 0.139

Stock

506,246

439,192

Authorized Distributors

Case/Package

SOP

Number of Pins

Logic Function

AND, D-Type, Flip-Flop

Number of Elements

Number of Bits per Element

Propagation Delay

16 ns

Frequency

95 MHz

Clock Edge Trigger Type

Positive Edge

Min Supply Voltage

2 V

Max Supply Voltage

6 V

Quiescent Current

4 µA

供应链

Country of OriginMainland China, Philippines, Thailand

Harmonized Tariff Schedule (HTS) Code8542.39.00.60

Introduction Date1996-04-09

Lifecycle StatusProduction (Last Updated: 5 years ago)

Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

描述

由其分销商提供的 onsemi MC74AC74DG 的描述。

4¦ÌA 10ns@ 5V,50pF , 2 2V 6V 24mA Set(Preset) and Reset AC 4.5pF 24mA 160MHz SOIC-14 1.75mm

Unikeyic (ICkey)

MC74AC74DG DUAL D TYPE FLIP FLOP IC, COMPLEMENTARY, 2 - 6 V, 14-PIN SOIC

RS (Formerly Allied Electronics)

Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC N Tube

Verical

FLIP-FLOP, D-TYPE, DUAL, 9.5NS, SOIC-14; Logic Family / Base Number: 74AC74; Flip-Flop Type: D; Propagation Delay: 9.5ns; Frequency: 160MHz; Output Current: 24mA; Logic Case Style: SOIC; No. of Pins: 14Pins; Trigger Type: Positi

Farnell

The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH

North Star Micro