onsemi MC100LVEL39DWG

Low Skew Clock Driver, 100LVEL Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20

Amplifiers- Audio 3.3V ECL Clock Generator

IC CLOCK GEN ECL 2/4 4/6 20SOIC

MC100LVEL39DWG, MOTOR DRIVER IC;

The MC100LVEL39 is a low skew 2/4 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. In addition by using the VBB output a sinusoidal source can be AC coupled into the device. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock therefore all associated specification limits are referenced to the negative edge of the clock input. Upon startup the internal flip-flops will attain a random state; therefore for systems which utilize multiple LVEL39s the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39 the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.