onsemi MC100LVE111FNG

Clock Buffer, Driver, Fanout, 9 Outputs, 3 V to 3.8 V, 28 Pins, PLCC

3.3 V ECL 1:9 Differential Clock Driver

Low Skew Clock Driver, 100LVE Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28

Clock Fanout Buffer 9-OUT 1-IN 1:9 28-Pin PLCC Tube

Amplifiers- Audio 3.3V ECL 1:9 DIFF Clock Driver

IC, SM, LOGIC, ECL, CLOCK GEN; Clock IC Type: Clock Driver; Frequency: 1.5GHz; No. of Outputs: 9Outputs; Supply Voltage Min: 3V; Supply Voltage Max: 3.8V; Clock IC Case Style: LCC; No. of Pins: 28Pins; Operating Temperature Min

The MC100LVE111 is a low skew 1-to-9 differential driver designed with clock distribution in mind. The MC100LVE111s function and performance are similar to the popular MC100E111 with the added feature of low voltage operation. It accepts one signal input which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The LVE111 is specifically designed modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 W even if only one side is being used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20 ps) of the output(s) being used which while not being catastrophic to most designs will mean a loss of skew margin. The MC100LVE111 as with most other ECL devices can be operated from a positive VCC supply in PECL mode. This allows the LVE111 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE111s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL parallel termination offers the lowest power