onsemi 74LVX74MTCX

Name: onsemi 74LVX74MTCX
Brand: onsemi
SKU: 74LVX74MTCX

74LVX Series 3.6 V Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

$ 0.199

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Distributor		SKU		Min	Pkg
Rochester Electronics		74LVX74MTCX	247,845					0.239	0.199	0.177	1d
DigiKey	3	74LVX74MTCXCT-ND	1,430	1	Cut Tape	0.470	0.327	0.253	0.216	0.216
Verical	8	74LVX74MTCX	100	22				0.237	0.196	0.179
Arrow Electronics	2	74LVX74MTCX	100	1		0.453	0.312	0.237	0.237	0.237
Newark	2	74LVX74MTCX	0	2500	Tape & Reel					0.219

数据表和文档

下载 onsemi 74LVX74MTCX 的数据表和制造商文档。

Master Electronics

Datasheet0 页0 年前

IHS

onsemi

Newark

Fairchild Semiconductor

库存历史记录

3 个月趋势:

-0.80%

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onsemi74LVX74MTCX

onsemi74LVX74MTC

Price @ 1000

$ 0.199

$ 0.155

Stock

1,774,472

443,570

Authorized Distributors

Case/Package

TSSOP

Number of Pins

Logic Function

AND, D-Type, Flip-Flop

Number of Elements

Number of Bits per Element

Propagation Delay

15 ns

Frequency

50 MHz

Clock Edge Trigger Type

Positive Edge

Min Supply Voltage

2 V

Max Supply Voltage

3.6 V

Quiescent Current

2 µA

供应链

Country of OriginPhilippines

Export Control Classification Number (ECCN) CodeEAR99

Harmonized Tariff Schedule (HTS) Code8542.39.00.01

Introduction Date1997-01-01

Lifecycle StatusProduction (Last Updated: 5 years ago)

Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

描述

由其分销商提供的 onsemi 74LVX74MTCX 的描述。

74LVX Series 3.6 V Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

Future Electronics

Tape & Reel (TR) 74LVX74 e4 74LVX flip flop 5mm 2V 13.2ns @ 3.3V 50pF 85MHz

Fly-Wing Technology

Flip Flop D-Type Pos-Edge 2-Element 14-Pin TSSOP W T/R

Verical

FLIP FLOP, D, -40 TO 85DEG C; Logic Family / Base Number: 74LVX74; Flip-Flop Type: D; Propagation Delay: 8.2ns; Frequency: 145MHz; Output Current: -; Logic Case Style: TSSOP; No. of Pins: 14Pins; Trigger Type: Positive Edge; IC

Farnell

The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q#) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S#D (Set) sets Q to HIGH level LOW input to C#D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C#D and S#D makes both Q and Q# HIGH

Fairchild Semiconductor