Texas Instruments CDCLVD2102

the cdclvd2102 clock buffer distributes two clock inputs (in0 in1) to a total of 4 pairs of differential lvds clock outputs (out0 out3). each buffer block consists of one input and 2 lvds outputs. the inputs can either be lvds lvpecl or lvcmos. the cdclvd2102 is specifically designed for driving 50- transmission lines. if driving the inputs in single ended mode the appropriate bias voltage (vac_ref) should be applied to the unused negative input pin. using the control pin (en) outputs can be either disabled or enabled. if the en pin is left open two buffers with all outputs are enabled if switched to a logical "0" both buffers with all outputs are disabled (static logical "0") if switched to a logical "1" one buffer with two outputs is disabled and another buffer with two outputs is enabled. view all in datasheet