Texas Instruments SN74LS293DR

Tape & Reel (TR) Obsolete 74LS293 Binary Counter divider circuit 70ns 3.9mm 5V 42MHz
$ 1.508

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Texas Instruments SN74LS293DR에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

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Datasheet10 페이지18년 전

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대체 부품

Price @ 1000
$ 1.508
$ 2.087
$ 2.087
Stock
67,467
187,033
187,033
Authorized Distributors
2
4
4
Case/Package
SOIC
SOIC
SOIC
Number of Pins
14
14
14
Logic Function
Counter
Counter
Counter
Direction
Up
Unidirectional
Unidirectional
Number of Elements
1
1
1
Number of Bits per Element
4
4
4
Reset
Synchronous
Synchronous
Synchronous
Clock Edge Trigger Type
Positive Edge
Positive Edge
Positive Edge
Frequency
42 MHz
42 MHz
42 MHz
Min Supply Voltage
4.75 V
4.75 V
4.75 V
Max Supply Voltage
5.25 V
5.25 V
5.25 V

관련 부품

Texas InstrumentsSN74LS92D
Divide-By-Twelve Counter 14-SOIC 0 to 70
Texas InstrumentsSN74LS93D
TEXAS INSTRUMENTS SN74LS93DLOGIC, 4-BIT BINARY COUNTER, 14SOIC
Texas InstrumentsSN74LS93DR
GULL WING DUAL Positive Edge Asynchronous Binary Counter IC 0C~70C 42MHz 0.008A 5V
MC74ACT163DG 4-STAGE BINARY COUNTER, UP COUNTER, 5V, 16-PIN SOIC
MC74ACT Series 4.5 V to 5.5 V Synchronous Presettable Binary Counter - SOIC-16
GULL WING DUAL Positive Edge Synchronous Binary Counter IC 0C~70C 40MHz 5V 3.9mm

설명

유통업체에서 제공한 Texas Instruments SN74LS293DR에 대한 설명입니다.

Tape & Reel (TR) Obsolete 74LS293 Binary Counter divider circuit 70ns 3.9mm 5V 42MHz
Counter/Divider Single 4-Bit Binary UP 14-Pin SOIC T/R
Counter Logic IC; Logic Family:LS; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Package/Case:14-SOIC; No. of Pins:14; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes; Output Type:TTL ;RoHS Compliant: Yes
The SN54290/SN74290, SN54LS290/SN74LS290, SN54293/SN74293, and SN54LS293/SN74LS293 counters are electrically and functionally identical to the SN5490A/SN7490A, SN54LS90/SN74LS90, SN5493A/SN7493A, and SN54LS93/SN74LS93, respectively. Only the arrangement of the terminals has been changed for the '290, 'LS290, '293, and 'LS293. Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '290 and 'LS290 and divide-by-eight for the '293 and 'LS293. All of these counters have a gated zero reset and the '290 and 'LS290 also have gated set-to-nine inputs for use in BCD nine's complement applications. To use the maximum count length (decade or four-bit binary) of these counters, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '290 and 'LS290 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

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