Texas Instruments 74ALVCH16820DLG4

Tube 74ALVCH16820 e4 74ALVCH flip flop 7.49mm 4.8ns @ 3.3V 50pF 150MHz 5.5ns

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Texas Instruments 74ALVCH16820DLG4에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

Texas Instruments

Datasheet12 페이지18년 전

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대체 부품

Price @ 1000
$ 1.44
$ 1.44
Stock
2,550
202,732
202,732
Authorized Distributors
0
2
2
Case/Package
SSOP
SSOP
SSOP
Number of Pins
56
56
56
Logic Function
D-Type, Flip-Flop
D-Type, Flip-Flop
D-Type, Flip-Flop
Number of Elements
1
1
1
Number of Bits per Element
10
10
10
Propagation Delay
5.5 ns
6.2 ns
6.2 ns
Frequency
150 MHz
150 MHz
150 MHz
Clock Edge Trigger Type
Positive Edge
Positive Edge
Positive Edge
Min Supply Voltage
1.65 V
1.65 V
1.65 V
Max Supply Voltage
3.6 V
3.6 V
3.6 V
Quiescent Current
-
-
-

설명

유통업체에서 제공한 Texas Instruments 74ALVCH16820DLG4에 대한 설명입니다.

Tube 74ALVCH16820 e4 74ALVCH flip flop 7.49mm 4.8ns @ 3.3V 50pF 150MHz 5.5ns
10-BIT TO 20-BIT D-TYPE FLIP-FLOP<AZ
IC FF D-TYPE SNGL 10BIT 56SSOP
This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation. The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or undriven inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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