onsemi MC100LVEL92DWG

MC100LV Series 5 V Triple PECL Input to LVPECL Output Translator - SOIC-20

LEVEL TRANSLATOR, PECL TO LVPECL, WSOIC; No. of Inputs: 3; Output Current: 50mA; Propagation Delay: 610ps; No. of Pins: 20Pins; Logic Case Style: WSOIC; Supply Voltage Min: 4.5V; Supply Voltage Max: 5.5V; Operating Temperature

Triple Pecl To Lvpecl Xlator Soic-20; Núm. De Entradas:3; Corriente De Salida:50Ma; Retardo De Propagación:610Ps; Núm. De Contactos:20; Circuito Lógico, Tipo:Soic; Tensión De Alimentación Mín.:4.5V; Tensión De Alimentación Máx.:5.5V |Onsemi MC100LVEL92DWG

The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply the LVCC supply is to be connected to the 3.3 V LVPECL supply and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with 0.01 F capacitors. The PECL VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.