onsemi MC100LVEL92DWG

onsemi logic level converter, Level Translators, SOIC-WBencapsulation, 20Pin

Translator, Triple PECL Input to LVPECL Output

Translator PECL to LVPECL 3-CH Unidirectional 20-Pin SOIC W Tube

MC100LVEL92DWG, BBG ECL TRNSLATR TRPL | ON Semiconductor MC100LVEL92DWG

PECL to LVPECL Translator, 3 Func, Complementary Output, ECL, PDSO20

e3 ACTIVE (Last Updated: 6days ago) 100LVEL92 Tin (Sn) level shifter translator 760ps 3.3V 800.987426mg -50mA

IC TRANSLATOR PECL TO LVPECL UNI-DIR SOIC-20

1 3 SOP-20-300mil Translators / Level Shifters ROHS

LEVEL TRANSLATOR, PECL TO LVPECL, WSOIC;

IC XLATOR TRP PECL-LVPECL 20SOIC

IC TRNSLTR UNIDIRECTIONAL 20SOIC

PECL TO LVPECL TRANSLATOR, 3 FUN

LEVEL TRANSLATOR, PECL TO LVPECL, WSOIC; No. of Inputs: 3; Output Current: 50mA; Propagation Delay: 610ps; No. of Pins: 20Pins; Logic Case Style: WSOIC; Supply Voltage Min: 4.5V; Supply Voltage Max: 5.5V; Operating Temperature

The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply the LVCC supply is to be connected to the 3.3 V LVPECL supply and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with 0.01 F capacitors. The PECL VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.