onsemi MC100LVEL34DG

Low Skew Clock Driver, 100LVEL Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO16

DUAL Obsolete GULL WING Surface Mount Clock Generator IC 4Weeks -40C~85C 9.9mm 39mA

Clock Generator 16-Pin SOIC Rail

3.3V ECL /2, /4, /8 Clock Generation Chip

3.3 V ECL ÷·2, ÷·4, ÷·8 Divider

Amplifiers- Audio HF ECL CLOCK GEN

MC100LVEL34DG, MOTOR DRIVER IC;

The MC100LVEL34 is a low skew 2 4 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The common enable (EN bar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore all associated specification limits are referenced to the negative edge of the clock input. Upon start-up the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internaldividers as well as multiple LVEL34s in a system.