onsemi 74ABT16500CMTD

18-Bit Universal Bus Transceivers with 3-STATE Outputs | IC UNIV BUS TXRX 18BIT 56TSSOP

Registered Bus Transceiver, ABT Series, 1-Func, 18-Bit, True Output, BICMOS, PDSO56

Surface Mount RoHS Compliant Transceiver Lead Free Universal Bus Transceiver -40C~85C 3mA 64mA 4.5V~5.5V 5.3ns

Bus XCVR Single 18-CH 3-ST 56-Pin TSSOP W Rail

IC UNIV BUS TXRX 18BIT 56TSSOP

The ABT16500 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA#), latch-enable (LEAB and LEBA), and clock (CLKAB# and CLKBA#) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB# is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB#. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA#, LEBA, and CLKBA#. The output enables are complementary (OEAB is active HIGH and OEBA# is active LOW) Product Highlights: Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode Flow-through architecture optimizes PCB layout Guaranteed latch-up protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability