onsemi MM74HCT574SJX

74HCT Series 5 V CMOS 3-STATE Octal D-Type Flip-Flop - SOIC-20
$ 0.613
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データシート & ドキュメント

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Datasheet10ページ20年前
Datasheet9ページ20年前
Datasheet0ページ0年前

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Fairchild Semiconductor

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代替部品

Price @ 1000
$ 0.613
$ 0.582
Stock
206,345
281,626
Authorized Distributors
2
4
Case/Package
SOP
SOP
Number of Pins
20
20
Logic Function
D-Type, Flip-Flop
D-Type, Flip-Flop
Number of Elements
1
1
Number of Bits per Element
8
8
Propagation Delay
38 ns
53 ns
Frequency
28 MHz
40 MHz
Clock Edge Trigger Type
Positive Edge
Positive Edge
Min Supply Voltage
4.5 V
4.5 V
Max Supply Voltage
5.5 V
5.5 V
Quiescent Current
8 µA
8 µA

サプライチェーン

Country of OriginPhilippines
Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1990-02-01
Lifecycle StatusProduction (Last Updated: 6 years ago)
LTB Date2020-10-01
LTD Date2021-04-01
Manufacturer Lifecycle StatusLIFETIME (Last Updated: 6 years ago)

関連部品

Texas InstrumentsCD74HCT273M96
High Speed CMOS Logic Octal D-Type Flip-Flop with eset 20-SOIC -55 to 125
Texas InstrumentsCD74HCT374M
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC Tube
Texas InstrumentsCD74HCT574M
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC Tube
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC W Tube
D Flip-Flop, HCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20
D Flip-Flop, HCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

説明

onsemi MM74HCT574SJXの詳細は販売業者から提供されます。

74HCT Series 5 V CMOS 3-STATE Octal D-Type Flip-Flop - SOIC-20
Tape & Reel (TR) 74HCT574 e3 74HCT flip flop 481.5mg 30ns @ 5V 50pF 33MHz 30ns
Ic,flip-Flop,octal,d Type,hct-Cmos,sop,20Pin,plastic Rohs Compliant: Yes
The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the outputs until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.

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