onsemi MC10E196FNG

Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28
$ 5.58
Obsolete

価格と在庫

データシート & ドキュメント

onsemi MC10E196FNGのデータシートとメーカー資料をダウンロードする。

IHS

Datasheet12ページ19年前

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3か月間の傾向:
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代替部品

Price @ 1000
$ 5.58
$ 3.454
$ 3.454
Stock
46,352
160,900
160,900
Authorized Distributors
3
2
2
Propagation Delay
3.63 ns
3.63 ns
3.63 ns
Number of Taps
127
127
127
Turn-On Delay Time
-
-
-
Frequency
1 GHz
-
-
Load Capacitance
-
-
-
Interface
-
-
-
Min Supply Voltage
4.2 V
4.2 V
4.2 V
Max Supply Voltage
5.7 V
5.7 V
5.7 V
Number of Channels
-
-
-
Case/Package
PLCC
PLCC
PLCC
Number of Pins
28
28
28

サプライチェーン

Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1993-12-01
Lifecycle StatusObsolete (Last Updated: 3 months ago)

関連部品

5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer
Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28
5.0 V ECL 1:6 Differential Clock/Data Fanout Buffer
MicrochipSY100E111AJY
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE) | IC CLK BUFFER 1:9 28PLCC
Analog DevicesDS12885QN+
DS12885 Series 5.5V Parallel Surface Mount Real Time Clock - PLCC-28
Analog DevicesDS12885Q+
parallel connection PLCC-28(11.5x11.5) Real-time Clocks (RTC) ROHS

説明

onsemi MC10E196FNGの詳細は販売業者から提供されます。

Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28
28-LCC (J-Lead) 10E MC10E196 Obsolete delay line IC 1.39ns 4.2V~5.7V 2006 0C~85C
Active Programmable Delay Line 1-IN 0.02ns ABS 3.88ns MAX 28-Pin PLCC Rail
5.0 V ECL Programmable Delay Chip
Audio & Video ICs 5V ECL Programmable Delay
Delay Line IC, Programmable, 128 Taps, 20 ps Delay/One Tap, 3.63 ns Total Delay, 4.2 V to 5.7 V, 28 Pins, PLCC
IC DELAY LINE 128TAP PROG 28PLCC
ACTIVE DELAY LINE, PROGRAMMABLE
IC, ECL PRGRMMABLE DELAY, 2.6ns, PLCC-28; Logic Type:Programmable Delay; Propagation Delay:2.6ns; Frequency:1GHz; Supply Voltage Min:4.2V; Supply Voltage Max:5.7V; Operating Temperature Min:0°C; Operating Temperature Max:85°C; MSL:- ;RoHS Compliant: Yes
The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6] which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input D7 is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs at the expense of only a single added line to the data bus for each additional PDC without the need for any external gating. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The 100 Series contains temperature compensation.

メーカーの別名

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