onsemi MC100E445FNG

100E Series 4-BIT Right Serial in Parallel Out Shift Register True Output PQCC28
$ 5.44
Obsolete

価格と在庫

データシート & ドキュメント

onsemi MC100E445FNGのデータシートとメーカー資料をダウンロードする。

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Technical Drawing1ページ5年前

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代替部品

Price @ 1000
$ 5.44
$ 3
Stock
45,333
225,100
Authorized Distributors
1
1
Case/Package
PLCC
PLCC
Number of Pins
28
28
Logic Function
Shift Register
Shift Register
Direction
-
-
Number of Elements
1
1
Number of Bits per Element
-
-
Propagation Delay
2.1 ns
2.1 ns
Min Supply Voltage
4.2 V
-
Max Supply Voltage
5.7 V
-

サプライチェーン

Country of OriginPhilippines
Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1994-01-01
Lifecycle StatusObsolete (Last Updated: 5 months ago)
LTB Date2007-12-31
LTD Date2008-06-30

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説明

onsemi MC100E445FNGの詳細は販売業者から提供されます。

100E SERIES 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER TRUE OUTPUT PQCC28
Shift Register Single 4-Bit Serial to Serial/Parallel 28-Pin PLCC Rail
The MC10/100E445 is an integrated 4 bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to 2.0 Gbps. The chip generates a divide by 4 and a divide by 8 clock for both 4 bit conversion and a two chip 8 bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0 the second to Q1 etc. Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the E446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles shifts the start bit for conversion from Qn to Qn1. For each required additional shift an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to swallow a clock pulse effectively shifting a bit from the Qn to the Qn1 output (see Timing Diagram B). The MODE input is used to select the conversion mode of the device. With the MODE input LOW or open the device will function as a 4 bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8 bit conversion scheme using two E445s. When cascaded in an 8 bit conversion scheme the devices will not operate at the 2.0 Gbps data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445.

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