onsemi 74VHC138MX

74VHC Series 5.5 V High Speed CMOS 3-to-8 Decoder/Demultiplexer - SOIC-16
$ 0.673
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データシート & ドキュメント

onsemi 74VHC138MXのデータシートとメーカー資料をダウンロードする。

IHS

Datasheet7ページ0年前
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Fairchild Semiconductor

onsemi

Augswan

Jameco

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代替部品

Price @ 1000
$ 0.673
$ 0.312
$ 0.312
Stock
356,898
324,440
324,440
Authorized Distributors
6
6
6
Case/Package
SOP
SOP
SOP
Number of Pins
16
16
16
Logic Function
Decoder, Demultiplexer, Demux
Decoder, Demultiplexer
Decoder, Demultiplexer
Number of Inputs
3
3
3
Number of Outputs
8
8
8
Number of Circuits
1
1
1
Low Level Output Current
8 mA
8 mA
8 mA
High Level Output Current
-8 mA
-8 mA
-8 mA
Supply Type
Single
Single
Single
Min Supply Voltage
2 V
2 V
2 V
Max Supply Voltage
5.5 V
5.5 V
5.5 V
Number of Channels
1
-
-

サプライチェーン

Country of OriginMainland China, Malaysia
Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1993-01-01
Lifecycle StatusProduction (Last Updated: 5 years ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

関連部品

74VHC Series 2 to 5.5 V CMOS 3-To-8 Line Decoder - SOIC-16
Texas InstrumentsSN74AHC138D
2V-to-5.5V 3-line to 8-line decoder and demultiplexer 16-SOIC -40 to 85
ON SEMICONDUCTOR MC74VHC138DG 3 LINE TO 8 LINE DECODER, SOIC-16
Texas InstrumentsSN74AHC138DR
2V-to-5.5V 3-line to 8-line decoder and demultiplexer 16-SOIC -40 to 85
Texas InstrumentsSN74AHC138DRE4
3-Line To 8-Line Decoder / Demultiplexer 16-SOIC -40 to 85
MC74VHCT138ADR2G, DECODER, 3-OF-8, INVERTING, 3 - 5.5 V, 16-PIN SOIC

説明

onsemi 74VHC138MXの詳細は販売業者から提供されます。

74VHC Series 5.5 V High Speed CMOS 3-to-8 Decoder/Demultiplexer - SOIC-16
AHC/VHC e3 74VHC138 1x 3:8 multiplexer circuit 18.5ns 2/5.5V 9.9mm 8mA 8mA
3-LINE TO 8-LINE DECODER, AHC/VHC Series, Inverted Output, CMOS, PDSO16
The VHC138 is an advanced high speed CMOS 3-to-8 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 binary select inputs (A0, A1 and A2) determine which one of the outputs (O#0-O#7) will go LOW. When enable input E3 is held LOW or either E#1 or E#2 is held HIGH, decoding function is inhibited and all outputs go HIGH. E3, E#1 and E#2 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

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