Texas Instruments SN74LVC373APWR

IC D-TYPE TRANSP SGL 8:8 20TSSOP D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP

74LVC373 Cut Tape (CT) LVC/LCX/Z 74LVC latch circuit 24mA 24mA 6.8ns 76.997305mg -40C~85C

10μA 1.5ns Non-inverting Tristate 1 1.65V 3.6V 24mA D-Type Transparent Latch LVC 1 24mA TSSOP-20 SMD mount，glue mount 1.2mm(height)

IC, 74LVC, SMD, 74LVC373, TSSOP20; Latch Type:D Type Transparent; Output Current:24mA; Propagation Delay:6.8ns; No. of Bits:8; IC Output Type:Tri State; Supply Voltage Range:1.65V to 3.6V; Logic Case Style:TSSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C; SVHC:No SVHC (20-Jun-2011); Base Number:74; IC Generic Number:74LVC373; Logic Function Number:74373; Logic IC Base Number:74373; Logic IC Family:LVC; Logic IC Function:Octal D-Type Transparent Latch (3-State); No. of Gates:8; No. of Inputs:1; Operating Temperature Max:85°C; Operating Temperature Min:-40°C; Output Type:Tri State; Package / Case:TSSOP; Supply Voltage:3.6V; Supply Voltage Max:3.6V; Supply Voltage Min:1.65V; Termination Type:SMD

The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.