onsemi NB6L295MNG

Active Programmable Delay Line 2-IN 0.011ns ABS 8.8ns MAX 24-Pin QFN EP Tube

NB Series 3.3 V 3 GHz Dual Channel Programmable Clock/Data Delay - QFN-24

onsemi , 256, 8.8ns, 24, CML,LVDS,LVPECL, LVPECL, LVCMOS, LVTTL, QFN

Active Delay Line, Programmable, 2-Func, 511-Tap, Complementary Output, ECL, QCC24

NB6L295MNG, DELAY LINE CIRCUIT, 256-TAPS 8.8NS 2-INPUT, 24-PIN QFN

LVPECL 2.375V~3.6V 6ns~17ns QFN-24-EP(4x4) Delay Lines ROHS

Dual Channel Programmable Delay Line with LVPECL Output

24-VFQFN Exposed Pad e3 ACTIVE (Last Updated: 2days ago) NB6L295 delay line circuit 4mm 3.2ns 6.2ns 2.5V 5Weeks

IC DELAY LINE 512TAP PROG 24QFN

IC DLY LN 512 TAP PROG 24-VFQFN

Programmable Delay Chip, 511Tap, 17Ns, Qfn24; No. Of Taps:511; Delay Time Per Tap:3.2Ns; Total Delay Time:17Ns; Supply Voltage Min:2.375V; Supply Voltage Max:3.6V; Digital Ic Case:Qfn; No. Of Pins:24Pins; Product Range:- Rohs Compliant: Yes |Onsemi NB6L295MNG

The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de-skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels PD0 and PD1 can be configured in one of two operating modes a Dual Delay or an Extended Delay. In the Dual Delay Mode each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel. The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore the Extended Delay path starts at the IN0/IN0 inputs flows through PD0 cascades to the PD1 and outputs through Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended Delay Mode. The required delay is accomplished by programming each delay channel via a 3-pin Serial Data Interface described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode. The Multi-Level Inputs can be driven directly by differential LVPECL LVDS or CML logic levels; or by single-ended LVPECL LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24-pin QFN Pb-free package. The NB6L295 is a member of the ECLinPS MAX family of high performance products.